EM39LV040
4M (512Kx8) Bits Flash Memory
SPECIFICATION
General Description
The EM39LV040 is a 4M bits Flash memory organized as 512K x 8 bits. The EM39LV040
uses a single 3.0 volt-only power supply for both Read and Write functions. Featuring high
performance Flash memory technology, the EM39LV040 provides a typical Byte-Program
time of 11 µsec and a typical Sector-Erase time of 40 ms. The device uses Toggle Bit or
Data# Polling to detect the completion of the Program or Erase operation. To protect against
inadvertent write, the device has on-chip hardware and software data protection schemes.
The device offers typical 100,000 cycles endurance and a greater than 10 years data retention.
The EM39LV040 conforms to JEDEC standard pin outs for x8 memories. It is offered in
package types of 32-lead PLCC, 32-pin TSOP, and known good die (KGD). For KGD, please
contact ELAN Microelectronics or its representatives for detailed information (see Appendix at
the bottom of this specification for Ordering Information).
The EM39LV040 devices are developed for applications that require memories with
convenient and economical updating of program, data or configurations, e.g., Networking
cards, CD-RW, Scanner, Digital TV, Electronic Books, GPS, Router/Switcher, etc.
Features
Single Power Supply
Full voltage range from 2.7 to 3.6 volts
for both read and write operations
Regulated voltage range: 3.0 to 3.6 volts
for both read and write operations
Sector-Erase Capability
Uniform 4Kbyte sectors
Sector-Erase Capability
Uniform 64Kbyte sectors
Read Access Time
Access time: 45, 55, 70 and 90 ns
Power Consumption
Active current: 5 mA (Typical)
Standby current: 1
µA
(Typical)
Erase/Program Features
Sector-Erase Time: 40 ms (Typical)
Chip-Erase Time:
40 ms (Typical)
Byte-Program Time: 11µs (Typical)
Chip Rewrite Time: 6 seconds (Typical)
End-of-Program or End-of-Erase
Detection
Data# Polling
Toggle Bit
CMOS I/O Compatibility
JEDEC Standard
Pin-out and software command sets
compatible with single-power supply
|Flash memory
High Reliability
Endurance cycles: 100K (Typical)
Data retention: 10 years
Package Option
32-pin PLCC
32-pin TSOP
This specification is subject to change without further notice. (07.22.2004 V1.0)
Page 1 of 21
EM39LV040
4M (512Kx8) Bits Flash Memory
SPECIFICATION
Functional Block Diagram
Flash
Mem ory Array
X-Decoder
Mem ory Address
Address Buffer &
Latches
Y-Decoder
CE#
OE#
W E#
Control Logic
I/O Buffers and Data Latches
DQ7-DQ0
Figure 0a:
Functional Block Diagram
Pin Assignments
32-Lead PLCC
A12 A15 A16 A18 V
DD
WE#
A17
4
3
2
1
32 31 30
29
28
27
26
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
5
6
7
8
9
10
11
12
13
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
32-Lead PLCC
Top View
25
24
23
22
21
14 15 16 17 18 19 20
DQ1DQ2 V
SS
DQ3DQ4DQ5DQ6
Figure 0b:
PLCC Pin Assignments
This specification is subject to change without further notice. (07.22.2004 V1.0)
Page 2 of 21
EM39LV040
4M (512Kx8) Bits Flash Memory
SPECIFICATION
32-Lead TSOP
A11
A9
A8
A13
A14
A17
W E#
V
DD
A18
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
V
SS
DQ2
DQ1
DQ0
A0
A1
A2
A3
Standard TSOP
Figure 0c:
TSOP Pin Assignments
Pin Description
Pin Name
A0–A18
DQ7–DQ0
CE#
OE#
WE#
V
DD
V
SS
19 addresses
Data inputs/outputs
Chip enable
Output enable
Write enable
3.0 volt-only single power supply
*
Device ground
Function
*
See Appendix for ordering information on speed options
and voltage supply tolerances.
Table 1:
Pin Description
This specification is subject to change without further notice. (07.22.2004 V1.0)
Page 3 of 21
EM39LV040
4M (512Kx8) Bits Flash Memory
SPECIFICATION
Device Operation
The EM39LV040 uses Commands to initiate the memory operation functions. The
Commands are written to the device by asserting WE# Low while keeping CE# Low. The
address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data
bus is latched on the rising edge of WE# or CE#, whichever occurs first.
Read
The Read operation of the EM39LV040 is controlled by CE# and OE#. Both have to be Low
for the system to obtain data from the outputs. CE# is used for device selection. When CE#
is high, the chip is deselected and only standby power is consumed. OE# is the output
control and is used to gate data from the output pins. The data bus is in high impedance state
when either CE# or OE# is high. Refer to the Read Cycle Timing Diagram in Figure 1 for
further details.
Byte Program
The EM39LV040 is programmed on a byte-by-byte basis. Before programming, the sector
where the byte is located; must be erased completely. The Program operation is
accomplished in three steps:
The first step is a three-byte load sequence for Software Data Protection.
The second step is to load byte address and byte data. During the Byte Program
operation, the addresses are latched on the falling edge of either CE# or WE#, whichever
occurs last; and the data is latched on the rising edge of either CE# or WE#, whichever
occurs first.
The third step is the internal Program operation which is initiated after the rising edge of
the fourth WE# or CE#, whichever occurs first. The Pro gram operation, once initiated,
will be completed within 16 µs. See Figures 2 and 3 for WE# and CE# controlled
Program operation timing diagrams respectively and Figure 12 for the corresponding
flowchart.
During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During
the internal Program operation, the host is free to perform additional tasks. Any command
issued during the internal Program operation is ignored.
This specification is subject to change without further notice. (07.22.2004 V1.0)
Page 4 of 21
EM39LV040
4M (512Kx8) Bits Flash Memory
SPECIFICATION
EM39LV040 Device Operation
Operation
Read
Program
Erase
Standby
Write Inhibit
Write Inhibit
Software Mode
Product
Identification
CE#
V
IL
V
IL
V
IL
V
IH
X
X
V
IL
OE#
V
IL
V
IH
V
IH
X
V
IL
X
V
IL
WE#
V
IH
V
IL
V
IL
X
X
V
IH
V
IH
DQ
D
OUT
D
IN
X
*
High Z
High Z/D
OUT
High Z/D
OUT
A
IN
A
IN
Address
Sector or Block address, XXH for
Chip-Erase
X
X
X
See Table 3
*
X can be V
IL
or V
IH
, but no other value.
Table 2:
EM39LV040 Device Operation
Write Command/Command Sequence
The EM39LV040 provides two software methods to detect the completion of a Program or
Erase cycle in order to optimize the system write cycle time. The software detection includes
two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode
is enabled after the rising edge of WE#, which initiates the internal Program or Erase
operation. The actual completion of the write operation is asynchronous with the system;
therefore, either a Data# Polling or Toggle Bit read may be simultaneously completed with the
write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data
may appear to conflict with either DQ7 or DQ6. In order to prevent such spurious rejection,
when an erroneous result occurs, the software routine should include an additional two times
loop to read the accessed location. If both reads are valid, then the device has completed the
write cycle, otherwise the rejection is valid.
Chip Erase
The EM39LV040 provides Chip-Erase feature, which allows the entire memory array to be
erased to logic “1” state. The Chip-Erase operation is initiated by executing a six-byte
command sequence with Chip-Erase command (10H) at address 5555H in the last byte
sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#,
whichever occurs first. During the Erase operation, the only valid reads are Toggle Bit and
Data# Polling. See Table 3 for the command sequence, Figure 6 for timing diagram, and
Figure 15 for the corresponding flowchart. Any command issued during the Chip-Erase
operation is ignored.
This specification is subject to change without further notice. (07.22.2004 V1.0)
Page 5 of 21
